The VLSI Final Project 4 - bit 4 function ALU
 
 
TABLE OF CONTENTS
 
   1.0    REPORT
 
2.0     SPICE
 
 2.1   Schematic of basic Inverter NOT
2.2 
 Schematic of basic NAND
NAND 
2.3 
 Schematic of basic NOR 
NOR 
2.4 
 Schematic of BUFFER
BUFFER 
2.5 
 Schematic of XOR   
(Transmission gates) 
XOR 
 2.6  
 Schematic of Adder  
(Transmission gates) 
 ADDER 
2.7  
 Schematic of Multiplexer
 MUX 
      2.8   Schematic of  4 - bit ALU block 
ALUblk 
      2.9  Schematic of  4 - bit ALU 
ALU 
 
  3.0     MAGIC
 
 3.1  Layout of basic Inverter         NOT
3.2 Layout of basic NAND         NAND
      3.3 Layout of basic NOR         NOR
      3.4 Layout of 2 input AND          AND
      3.5 Layout of 2 input OR          OR
      3.6 Layout of 3 input AND          AND3
      3.7  Layout of 4 input OR         OR4
      3.8 Layout of XOR  (Transmission gates)         XOR
      3.9 Layout of Adder (Transmission gates)         ADDER
      3.10 Layout of Multiplexer          MUX
      3.11 Layout of  BUFFER         BUFFER
      3.12  Layout of  4 - bit ALU          ALU 
 
 
4. .MAG FILES
 
4asalu.mag asand.mag asmux.mag asnot.mag asxor.mag asor.mag asnor.mag
asbuffer.mag asnand.mag asor4.mag asnand3.mag astgadder.mag asalu.mag
 
5. CONCLUSION
 
 
 
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