CONCLUSION
 
 
 
After extraction of the full 4 bit ALU it is noted that its CIR file had some floating points. We went back into the layout anddetected the floating points and painted the open the contacts .Finally we iteradted the whole circuit and at present there are no floating points and errors.

The ALU is running for certain conditions and a bit more of testing is required.After simulating the schematics it was found that the overall worst case delay (the delay across the ADDER for input rise and fall times of 200ps ) was coming to 9.3ns and the output rise anf fall times was 1.9ns and 1.7 ns respectively.

It was a great learning  experience where in we had an on hand exposure to the way circuits are designed and simulated from the basic gates in PSPICE to designing the layout in MAGIC and finally extracting it to be tested in PSPICE..