OBJECTIVE

This is a project which involved designing a'4 BIT 4 FUNCTION ARITHMETIC AND LOGIC UNIT (ALU)'.

FUNCTIONS OF THE ARITHMETIC AND LOGIC UNIT

The four functions of the ALU are :

• To calculate the SUM and CARRY of  two 4 bit numbers using an ADDER.
• To calculate the logical NAND of two 4 bit input numbers using a 4 bit NAND gate.
• To calculate the logical NOR of two 4 bit input numbers using a 4 bit NOR gate.
• To calculate the logical NOT of a 4 bit number which in this case is the input B.

Following were the design constraints which were to be considered  while designing the ALU:

• Supply Voltage ,Vdd=3.3 V.
• External loads of 100fF(in addition to all internal parasitics).
• Input signals rise and fall times < 200ps.
• Output signals rise and fall times < 2ns.

1) The design was started by first  trying to find the critical paths (i.e.) the paths where there would be a large delay.
    As a result we initially  concentrated on designing the 4 bit ADDER.It was decided to use a 'RIPPLE -CARRY ADDER'
    as it is the most simplest of all ADDERS . There are a number of ways by which  a 4 bit ADDER can be designed.
    Initially a  full ADDER was designed using combinational logic.The XOR gate using combinational logic can be seen by
    clicking here.

2) The number of transistors in the ADDER  using combinational logic are around 62 as 4, 2 input NAND gates  were used for
    the XOR gates  and  the delay for a sizing of  wn=3u and wp=9u was 4.342 nsec.As a result in order to decrease the          number of   transistors it was  decided to use XOR gates using 'TRANSMISSION GATES'.By using transmission gates the number   of transisitor's decreased to 18 transistors .

3) The Multiplexer was designed using combinational logic.The number of transistors were more in this design and hence a
    design using transmission gate was tried .But the design would not work and hence we decided to continue with the
    combinational logic.

4) We have used an overall sizing of Wn=3u and Wp=9u as the the minimum sizing that is allowed according to mosis rules.
     The rise times and the fall times  with minimum sizing was not according to required rise and fall times and hence we decided
     to use buffers at each output.This has helped to decrease the rise and fall times drastically.